NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1092 / 1379

Table 42-3. SCG modes of operation (continued)
Mode Description
In FIRC mode, SCGCLKOUT and system clocks are derived from the fast internal reference clock.
Four frequency range settings are available for FIRC clock as described in the FIRC[RANGE]
register definition. Changes to FIRC range settings will be ignored when FIRC clock is enabled.
Information regarding FIRC operation during normal and low power stop modes is found in the
"Stop" row of this table .
Sys PLL (SPLL) Sys PLL (SPLL) mode is entered when all the following conditions occur:
• RUN MODE: 0110 is written to RCCR[SCS].
VLRUN MODE: Invalid mode. Programming SCG into SPLL mode will be ingored.
HSRUN MODE: 0110 is written to HCCR[SCS].
• SPLLEN = 1
• SPLLVLD = 1
In SPLL mode, the SCGCLKOUT and system clocks are derived from the output of PLL which is
controlled by either the System Oscillator (SOSC) clock or the Fast internal reference clock (FIRC).
The selected PLL clock frequency locks to a multiplication factor, as specified by its corresponding
SCG_SPLLCFG[MULT], times the selected PLL reference frequency. The PLL's programmable
reference divider must be configured to produce a valid PLL reference clock. This divide value is
defined by the SCG_SPLLCFG[PREDIV] bits.
Information regarding SPLL operation during normal and low power stop modes is found in the
"Stop" row of this table .
Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power
mode assignments, see the chapter that describes how modules are configured and SCG behaviour
during Stop recovery. Entering Stop mode, all SCG clock signals are static except the following
clocks which can continue to run and stay enabled in the following cases:
SIRCCLK is available in Normal Stop and VLPS mode when all the following conditions become
true:
• SIRCCSR[SIRCEN] = 1
• SIRCCSR[SIRCSTEN] = 1
• SIRCCSR[SIRCLPEN] = 1 in VLPS
FIRCCLK is available only in Normal Stop mode when all the following conditions become true:
• FIRCCSR[FIRCEN] = 1
• FIRCCSR[FIRCSTEN] = 1
SOSCLK is available in following low power stop modes (Normal Stop, VLPS, LLS) when all the
below conditions are true. In VLLS stop mode, SOSCLK is disabled.
• SOSCCSR[SOSCEN] = 1
• SOSCCSR[SOSCSTEN] = 1
• SOSCCSR[SOSCLPEN] = 1 (required only for Low Power Stop modes (VLPS and LLS)
SPLLCLK is available in Normal Stop mode when all the following conditions are true:
• SPLLCSR[SPLLEN] = 1
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1092 NXP Semiconductors