NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1196 / 1379

Field Function
5-0
SEL0
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the
Select Bit Fields table in the Features section for bit field information.
47.2.1.10 TRGMUX CMP1 (TRGMUX_CMP1)
47.2.1.10.1 Address
Register Offset
TRGMUX_CMP1 40027030h
TRGMUX Register
47.2.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LK
Rese
rved
Reserved Reserved Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved Reserved Reserved SEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
47.2.1.10.3 Fields
Field Function
31
LK
This bit shows whether the register can be written or not.
0 - Register can be written.
1 - Register cannot be written until the next system Reset.
30
—
This read-only bit field is reserved and always has the value 0.
29-24
—
This read-only bit field is reserved and always has the value 0.
23-22 This read-only bit field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1196 NXP Semiconductors