NXP Semiconductors K32 L2A Series, Reference Manual, Page: 305 / 1379

Table 14-54. Configuring the QuadSPI module
Configure
QuadSPI at Procedure Clock updates during QuadSPI
module configuration
6. After start-up, ROM code reads the QCB from address
0 of the external SPI flash and then configures the
QuadSPI according to the QCB.
7. Now, the Kinetis Bootloader is able to access all
connected SPI flash devices.
The QuadSPI module will be configured automatically out of
reset, if the QCB is already present and the BOOTSRC_SEL
field (bits [7:6]) in FOPTregister at the address 0x40D equals
to “0’b10”.
NOTE
The user application boot from QuadSPI in XIP mode should
not change the QuadSPI source clock from what ROM has
configured (as shown in the previous table); otherwise a hard
fault may occur. However, the QuadSPI source clocks (listed in
the next table) can be changed successfully, if the application
avoids shutting down the QSPI clock during clock switching;
for example, if the clock switch related codes are relocated in
either internal flash or SRAM.
Table 14-55. Register value updates when the QuadSPI module is configured at start-up
Register Field Value Description
MCG_C7 OSCSEL 2 IRC48M is chosen as external reference clock
MCG_C1 FRDIV 6 Combined with MCG_C2[RANGE] to divide IRC48M with 1280
MCG_C4 DMX32 0
MCG_C4 DRST_DRS 3 Combined with MCG_C4[DMX32] to multiply divided clock with
2560 , then MCGOUT clock is equal to 96 MHz.
MCG_C6 PLLS 0 Disable PLL
MCG_C1 IREFS 0 Switch to external reference clock
SIM_CLKDIV1 OUTDIV1 0
SIM_CLKDIV1 OUTDIV2 1
SIM_CLKDIV1 OUTDIV3 1
SIM_CLKDIV1 OUTDIV4 3
QUADSPII0_SOCCR QSPISRC 1 MCGFLL clock is selected as the clock source for QuadSPI module
14.4.3.4 Access external SPI flash devices using QuadSPI module
The Kinetis Bootloader supports access to external SPI flash devices using the following
commands:
Chapter 14 Kinetis ROM Bootloader
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 305