NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1360 / 1379

WDOGx_CS field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
15
WIN
Watchdog Window
This write-once bit enables window mode. See the Window mode section.
0 Window mode disabled.
1 Window mode enabled.
14
FLG
Watchdog Interrupt Flag
This bit is an interrupt indicator when INT is set in control and status register 1. Write 1 to clear it.
0 No interrupt occurred.
1 An interrupt occurred.
13
CMD32EN
Enables or disables WDOG support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words
0 Disables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words
1 Enables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words
12
PRES
Watchdog Prescalar
This write-once bit enables a fixed 256 pre-scaling of watchdog counter reference clock. (The block
diagram shows this clock divider option.)
0 256 prescalar disabled.
1 256 prescalar enabled.
11–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–8
CLK
Watchdog Clock
This write-once field indicates the clock source that feeds the watchdog counter. See the Clock source
section.
00 Bus clock.
01 Internal low-power oscillator (LPOCLK).
10 8 MHz internal reference clock.
11 External clock source.
7
EN
Watchdog Enable
This write-once bit enables the watchdog counter to start counting.
0 Watchdog disabled.
1 Watchdog enabled.
6
INT
Watchdog Interrupt
This write-once bit configures the watchdog to immediately generate an interrupt request upon a reset-
triggering event (timeout or illegal write to the watchdog), before forcing a reset. After the interrupt vector
fetch (which comes after the reset-triggering event), the reset occurs after a delay of 128 bus clocks.
0 Watchdog interrupts are disabled. Watchdog resets are not delayed.
1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt
vector fetch.
Table continues on the next page...
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1360 NXP Semiconductors