NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1331 / 1379

USBx_CLK_RECOVER_CTRL field descriptions (continued)
Field Description
adjusting the trim fine value is different during these 2 phases. The step in rough phase is larger than that
in tracking phase. Switch back to rough stage whenever USB bus reset or bus resume occurs.
0 Always works in tracking phase after the first time rough to track transition (default)
1 Go back to rough stage whenever bus reset or bus resume occurs
5
RESTART_
IFRTRIM_EN
Restart from IFR trim value
FIRC has a default trim fine value whose default value is factory trimmed (the IFR trim value). Clock
recover block tracks the accuracy of the clock 48Mhz and keeps updating the trim fine value accordingly
0 Trim fine adjustment always works based on the previous updated trim fine value (default)
1 Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module
enable is desasserted
4–3
Reserved
This field is reserved.
2
Reserved
This field is reserved.
This bit is for NXP use only. Customers should not change this bit from its default state.
1
Reserved
This field is reserved.
This bit is for NXP use only. Customers should not change this bit from its default state.
0
Reserved
This field is reserved.
Default should not be changed
51.4.31 FIRC oscillator enable register
(USBx_CLK_RECOVER_IRC_EN)
This register is reserved.
Address: 4005_5000h base + 144h offset = 4005_5144h
Bit 7 6 5 4 3 2 1 0
Read 0
Write
Reset
0 0 0 0 0 0 0 0
USBx_CLK_RECOVER_IRC_EN field descriptions
Field Description
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1331