NXP Semiconductors K32 L2A Series, Reference Manual, Page: 419 / 1379

NOTE
For correct operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Minor loop offsets are address offset values added to the final source address
(TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion.
When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the
final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR),
or to both prior to the addresses being written back into the TCD. If the major loop is
complete, the minor loop offset is ignored and the major loop address offsets
(TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR
and TCDn_DADDR values.
When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion
of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to
specify the minor loop offset should be applied to the source address (TCDn_SADDR)
upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop
offset should be applied to the destination address (TCDn_DADDR) upon minor loop
completion, and the sign extended minor loop offset value (MLOFF). The same offset
value (MLOFF) is used for both source and destination minor loop offsets. When either
minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES field is reduced
to 10 bits. When both minor loop offsets are disabled (SMLOE cleared and DMLOE
cleared), the NBYTES field is a 30-bit vector.
When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
assigned to the NBYTES field.
Address: 4000_8000h base + 0h offset = 4000_8000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ACTIVE
Reserved 0
CX ECX
W
Reset
0 x* x* x* x* x* x* x* 0 0 0 0 0 0 0 0
Chapter 20 Enhanced Direct Memory Access (eDMA)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 419