NXP Semiconductors K32 L2A Series, Reference Manual, Page: 301 / 1379

Table 14-52. Configuration fields in QSPI config block
(continued)
Offset Size
(bytes)
Configuration Field Description
1 Pins for both QSPI0A and QSPI0B are enabled
2 Only pins for QSPI0A are enabled; pins are on
PORTC.
0x54 – 0x57 4 ddr_mode_enable Enable DDR mode
0 DDR mode is disabled
1 DDR mode is enabled
0x58 – 0x5b 4 dqs_enable Enable DQS
0 DQS is disabled
1 DQS is enabled
0x5c – 0x5f 4 parallel_mode_enable Enable Parallel Mode
0 Parallel mode is disabled
1 Parallel mode is enabled
1
0x60 – 0x63 4 portA_cs1 Enable QuadSPI0A_CS1
0 QuadSPI0A_CS1 is disabled
1 QuadSPI0A_CS1 is enabled
portA_cs1 field must be set to 1 if sflash_A2_size is
not equal to 0.
0x64 – 0x67 4 portB_cs1 Enable QuadSPI0B_CS1
0 QuadSPI0B_CS1 is disabled
1 QuadSPI0B_CS1 is enabled
portB_cs1 field must be set to 1 if sflash_B2_size is
not equal to 0.
0x68 – 0x6b 4 fsphs Full Speed Phase selection for SDR instructions
0 Select sampling at non-inverted clock
1 Select sampling at inverted clock
0x6c – 0x6f 4 fsdly Full Speed Delay selection for SDR instructions
0 One clock cycle delay
1 Two clock cycles delay.
0x70 – 0x73 4 ddrsmp DDR sampling point
Valid range: 0 - 7
0x74 – 0x173 4 look_up_table Look-up-table for sequences of instructions
0x174 – 0x177 4 column_address_space Column Address Space
Defines the width of the column address
0x178 – 0x17b 4 config_cmd_en Enable additional configuration command
0 Additional configuration command is not needed
1 Additional configuration command is needed
0x17c – 0x18b 16 config_cmds IPCR arrays for each connected SPI flash
Table continues on the next page...
Chapter 14 Kinetis ROM Bootloader
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 301