NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1112 / 1379

SMC_PARAM field descriptions (continued)
Field Description
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
ELLS
Existence of LLS feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
2–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
EHSRUN
Existence of HSRUN feature
This static bit states whether or not the feature is available on the device.
0 The feature is not available.
1 The feature is available.
44.3.3 Power Mode Protection register (SMC_PMPROT)
This register provides protection for entry into any low-power run or stop mode. The
enabling of the low-power run or stop mode occurs by configuring the Power Mode
Control register (PMCTRL).
The PMPROT register can be written only once after any system reset.
If the MCU is configured for a disallowed or reserved power mode, the MCU remains in
its current power mode. For example, if the MCU is in normal RUN mode and AVLP is
0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and
PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the Reset
section details for more information.
Address: 4007_E000h base + 8h offset = 4007_E008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register descriptions
K32 L2A Reference Manual, Rev. 2, 01/2020
1112 NXP Semiconductors