NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1187 / 1379

Field Function
—
21-16
SEL2
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. Refer to the
Select Bit Fields table in the Features section for bit field information.
15-14
—
This read-only bit field is reserved and always has the value 0.
13-8
SEL1
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. Refer to the
Select Bit Fields table in the Features section for bit field information.
7-6
—
This read-only bit field is reserved and always has the value 0.
5-0
SEL0
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the
Select Bit Fields table in the Features section for bit field information.
47.2.1.3 TRGMUX LPIT0 (TRGMUX_LPIT0)
47.2.1.3.1 Address
Register Offset
TRGMUX_LPIT0 40027004h
TRGMUX Register
47.2.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LK
Rese
rved
SEL3 Reserved SEL2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved SEL1 Reserved SEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 47 Trigger MUX Control (TRGMUX)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1187