NXP Semiconductors K32 L2A Series, Reference Manual, Page: 78 / 1379

3.8.2.2 PIT/ADC triggers
PIT triggers can be selected as ADCx trigger sources. For more details, see the Trigger
Mux.
3.8.2.3 LPIT/TPM Triggers
LPIT triggers are selected as TPMx trigger sources in the TRGMUX module. For more
details, refer to
TRGMUX chapter.
Low Power Timer (LPTMR)
3.8.3.1 LPTMR instantiation information
This device has two low-power timers: LPTMR0 and LPTMR1. Both allow operation
during all power modes. LPTMR0 is accessed via AIPS0. LPTMR1 is accessed via
AIPS1.
The LPTMR can operate as a real-time interrupt or pulse accumulator. It includes a 2
N
prescaler (real-time interrupt mode) or a glitch filter (pulse accumulator mode).
An LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO,
ERCLK, or an external 32.768 kHz crystal. In VLLS0 mode, the clocking option is
limited to an external pin with the OSC configured for bypass (external clock) operation.
An interrupt is generated (and the counter may reset) when the counter equals the value
in the 16-bit compare register.
3.8.3.2 LPTMR pulse counter input options
LPTMRx_CSR[TPS] configures the input source used in pulse counter mode. The
following table shows the chip-specific input assignments for this field.
LPTMRx_CSR[TPS] Pulse counter input
number
LPTMR0 input source LPTMR1 input source
00 0 CMP0 output LPTMR0 trigger
01 1 LPTMR0_ALT1 pin LPTMR1_ALT1 pin
10 2 LPTMR0_ALT2 pin LPTMR1_ALT2 pin
11 3 LPTMR0_ALT3 pin LPTMR1_ALT3 pin
3.8.3
Low Power Timer (LPTMR)
K32 L2A Reference Manual, Rev. 2, 01/2020
78 NXP Semiconductors