NXP Semiconductors K32 L2A Series, Reference Manual, Page: 121 / 1379

Table 5-4. DIVCORE_CLK and DIVSLOW_CLK out-of-reset configuration
FTFA_FOPT[4:0] DIVCORE_CLK DIVSLOW_CLK Execution mode
00 0x7 (divide by 8) 0x1 (divide by 2) VLPR
01 0x3 (divide by 4) 0x1 (divide by 2) VLPR
10 0x1 (divide by 2) 0x1 (divide by 2) RUN
11 0x0 (divide by 1) 0x1 (divide by 2) RUN
This gives the user flexibility in selecting between a lower frequency, low-power boot
option and higher frequency, higher power during and after reset. The flash erased state
defaults to fast clocking mode, since these bits reside in flash, which is logic 1 in the
flash erased state. To enable a lower power boot option, program the appropriate bits in
FTFA_FOPT. During the reset sequence, if either of the control bits is cleared, the
system is in a slower clock configuration. Upon any system reset, the clock dividers
return to this configurable reset state. The factory default reset clock for core/system
clock is 8MHz from SIRC.
5.13 Clock gating
Clock gating of modules helps users to only consume power for modules that are needed
for their end application. The clock to each module will have the capability to be gated on
or off via a programmable register. Each peripheral has independent clock gating for both
the peripheral interface clock and the peripheral functional clock. This clock gating is
controlled via the peripheral’s PCCn register. Clearing PCCn[CGC] disables the
peripheral interface clock, and clearing of PCCn[PCS] disables the peripheral functional
clock. The SCG also has clock gating functionality of the peripheral functional clocks,
which can be used to gate several peripheral functional clocks via the xxxDIV[xxxDIVy]
fields. The DIVCORE_CLK and DIVSLOW_CLK are always enabled in the various
RUN and Wait modes. If these are not used in low power stop modes, then they will be
disabled via the SMC and PMC modules.
Both the Core Clock and Slow (Flash) Clocks have associated clock gates in the SCG.
5.14 Flash Memory Clock
The embedded Flash memory has a maximum operating frequency of 25Mhz. This
device uses the DIVSLOW_CLK from the SCG. This clock output should not exceed
25MHz for reliable flash operation.
Chapter 5 Clock Distribution
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 121