NXP Semiconductors K32 L2A Series, Reference Manual, Page: 759 / 1379

• For each timer channel that is to be enabled, configure the timer mode of operation
(MODE bits), Trigger source selection (TRG_SEL & TRG_SRC) and Trigger
control bits (TROT, TSOT, TSOI bits) in the TCTRLn register.
• Configure the channels that are to be chained by setting the CHAIN bit in the
corresponding channel's TCTRLn register.
• For channels configured in Compare Mode, set the timer timeout value by
programming the appropriate value in TVAL register for those channels.
• Configure TIEn bits in MIER register for those channels which are required to
generate interrupt on timer timeout.
• Configure the low power mode functionality of the module by setting the DBG_EN
and DOZE_EN bits in the MCR register. This is common to all timer channels.
• Enable the channel timers by setting the corresponding T_EN bit in the
corresponding channel's TCRTLn register.
• For channels configured in Capture Mode, the timer value can be read from TVALn
register when channel timeout occurs.
• At any time, the current value of the timer for any channel can be read by reading the
corresponding channel's CVALn register.
• The timer interrupt flag bits (TIFn) in MSR register get asserted on timer timeout.
These bits can be cleared by writing '1' to them.
28.4.2 Timer Modes
The timer mode is configured by setting an appropriate value in the MODE bits in
TCTRLn register. The timer modes supported are:
• 32-bit Periodic Counter: In this mode the counter will load and then decrement down
to zero. It will then set the timer interrupt flag and assert the output pre-trigger.
• Dual 16-bit Periodic Counter: In this mode, the counter will load and then the lower
16-bits will decrement down to zero, which will assert the output pre-trigger. The
upper 16-bits will then decrement down to zero, which will negate the output pre-
trigger and set the timer interrupt flag.
• 32-bit Trigger Accumulator: In this mode, the counter will load on the first trigger
rising edge and then decrement down to zero on each trigger rising edge. It will then
set the timer interrupt flag and assert the output pre-trigger.
• 32-bit Trigger Input Capture: In this mode, the counter will load with 0xFFFF_FFFF
and then decrement down to zero. If a trigger rising edge is detected, it will store the
inverse of the current counter value in the load value register, set the timer interrupt
flag and assert the output pre-trigger.
The timer operation is further controlled by Trigger Control bits (TSOT, TSOI, TROT)
which control the timer load, reload, start and restart of the timers.
Chapter 28 Low Power Interrupt Timer (LPIT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 759