NXP Semiconductors K32 L2A Series, Reference Manual, Page: 573 / 1379

Transmit shifters must be configured to load on the first shift when the timer is
configured to insert a stop bit on each compare.
When the condition configured by timer disable (TIMDIS) is detected, the following
events occur.
• Timer counter will reload the current value of the Compare Register and start
decrementing as configured by TIMDEC.
• Timer output will clear.
• Transmit shifters controlled by this timer will output their stop bit value (if
configured by SSTOP).
• Receive shifters controlled by this timer will store the contents of the shift register in
their shift buffer, as configured by SSTOP.
If the timer stop bit is enabled, the timer counter will continue decrementing until the
next rising edge of the shift clock is detected, at which point it will finish. A timer enable
condition can be detected in the same cycle as a timer disable condition (if timer stop bit
is disabled), or on the first rising edge of the shift clock after the disable condition (if stop
bit is enabled). Receive shift registers will stop bit enabled will store the contents of the
shift register into the shift buffer and verify the state of the input data on the configured
shift edge while the timer is in the stop state condition. If there is no configured edge
between the timer disable and the next rising edge of the shift clock then the final store
and verify do not occur.
22.3.3 Pin operation
The pin configuration for each timer and shifter can be configured to use any FlexIO pin
with either polarity. Each timer and shifter can be configured as an input, output data,
output enable or bidirectional output. A pin configured for output enable can be used as
an open drain (with inverted polarity, since the output enable assertion would cause logic
zero to be output on the pin) or to control the enable on the bidirectional output. Any
timer or shifter could be configured to control the output enable for a pin where the
bidirectional output data is driven by another timer or shifter.
In addition, shifters can also be configured to use multiple FlexIO pins in parallel using
the SHIFTCFG[PWIDTH] field. PWIDTH is used to configure the following settings of
a shifter:
1. Number of bits shifted per Shift clock.
2. Number of pins driven by the shifter per Shift clock (only on shifters supporting
parallel transmit i.e. SHIFTER0, SHIFTER4).
3. Number of pins sampled by the shifter per Shift clock (only on Shifter supporting
parallel receive i.e. SHIFTER3, SHIFTER7).
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 573