NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1347 / 1379

53.1.2 Features
• Programmable trim register with 0.5 mV steps in 1.2V mode and 1.5mV steps in
2.1V mode; upon reset, the trim register is automatically loaded with a factory-
trimmed value
• Programmable buffer mode selection:
• Off
• Bandgap enabled/standby (output buffer disabled)
• Low power buffer mode (output buffer enabled)
• High power buffer mode (output buffer enabled)
• Selectable 1.2V or 2.1V output at room temperature
• Dedicated output pin, VREF_OUT
53.1.3 Modes of Operation
The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The
Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait
(VLPW) and Very Low Power Stop (VLPS). If it is desired to use the VREF regulator
and/or the chop oscillator in the very low power modes, the system reference voltage
(also referred to as the bandgap voltage reference) must be enabled in these modes. Refer
to the chip configuration details for information on enabling this mode of operation.
Having the VREF regulator enabled does increase current consumption. In very low
power modes it may be desirable to disable the VREF regulator to minimize current
consumption. Note however that the accuracy of the output voltage will be reduced (by as
much as several mVs) when the VREF regulator is not used.
NOTE
The assignment of module modes to core modes is chip-
specific. For module-to-core mode assignments, see the chapter
that describes how modules are configured.
Chapter 53 Voltage Reference (VREF)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1347