NXP Semiconductors K32 L2A Series, Reference Manual, Page: 765 / 1379

29.1.5 Signal Descriptions
Signal Description I/O
SCK Serial clock. Input in slave mode, output
in master mode. I/O
PCS[0] Peripheral Chip Select. Input in slave
mode, output in master mode. I/O
PCS[1] / HREQ Peripheral Chip Select or Host Request.
Host Request pin is selected when
HREN=1 and HRSEL=0. Input in either
slave mode or when used as Host
Request, output in master mode. I/O
PCS[2] / DATA[2] Peripheral Chip Select or data pin 2
during quad-data transfers. Input in
slave mode, output in master mode,
input in quad-data receive transfers,
output in quad-data transmit transfers. I/O
PCS[3] / DATA[3] Peripheral Chip Select or data pin 3
during quad-data transfers. Input in
slave mode, output in master mode,
input in quad-data receive transfers,
output in quad-data transmit transfers. I/O
SOUT / DATA[0] Serial Data Output. Can be configured
as serial data input signal. Used as data
pin 0 in quad-data and dual-data
transfers. I/O
SIN / DATA[1] Serial Data Input. Can be configured as
serial data output signal. Used as data
pin 1 in quad-data and dual-data
transfers. I/O
Memory Map and Registers
LPSPI memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_E000 Version ID Register (LPSPI2_VERID) 32 R 0100_0004h 29.2.1/767
4003_E004 Parameter Register (LPSPI2_PARAM) 32 R See section 29.2.2/768
4003_E010 Control Register (LPSPI2_CR) 32 R/W 0000_0000h 29.2.3/769
4003_E014 Status Register (LPSPI2_SR) 32 R/W 0000_0001h 29.2.4/770
4003_E018 Interrupt Enable Register (LPSPI2_IER) 32 R/W 0000_0000h 29.2.5/772
4003_E01C DMA Enable Register (LPSPI2_DER) 32 R/W 0000_0000h 29.2.6/773
4003_E020 Configuration Register 0 (LPSPI2_CFGR0) 32 R/W 0000_0000h 29.2.7/774
Table continues on the next page...
29.2
Chapter 29 Low Power Serial Peripheral Interface (LPSPI)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 765