NXP Semiconductors K32 L2A Series, Reference Manual, Page: 738 / 1379

27.3.3 Slave Mode
The LPI2C slave logic operates independently from the master logic to perform all slave
mode transfers on the I2C bus.
27.3.3.1 Address Match
The LPI2C slave can be configured to match one of two addresses using either 7-bit or
10-bit addressing modes for each address, or to match a range of addresses in either 7-bit
or 10-bit addressing modes. Separately, it can be configured to match the General Call
Address or the SMBus Alert Address and generate appropriate flags. The LPI2C slave
can also be configured to detect the high speed mode master code and to disable the
digital filters and output valid delay time until the next STOP condition is detected.
Once a valid address is matched, the LPI2C slave will automatically perform slave-
transmit or slave-receive transfers until a NACK is detected (unless IGNACK is set), a
bit error is detected (the LPI2C slave is driving SDA, but a different value is sampled), or
a (repeated) START or STOP condition is detected.
27.3.3.2 Transmit and Receive
The transmit and receive data registers are double buffered and only update during a
slave-transmit and slave-receive transfer respectively. The slave address that was
received can be configured to be read from either the receive data register (for example,
when using DMA to transfer data) or from the address status register. The transmit data
register can be configured to only request data once a slave-transmit transfer is detected
or to request new data whenever the transmit data register is empty.
The transmit data register should only be written when the transmit data flag is set. The
receive data register should only be read when the received data flag is set (or the address
valid flag is set and RXCFG=1). The address status register should only be read when the
address valid flag is set.
27.3.3.3 Clock Stretching
The LPI2C slave supports many configurable options for when clock stretching is
performed. The following conditions can be configured to perform clock stretching.
• During 9th clock pulse of address byte and address valid flag is set.
• During 9th clock pulse of slave-transmit transfer and transmit data flag is set.
• During 9th clock pulse of slave-receive transfer and receive data flag is set.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
738 NXP Semiconductors