NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1316 / 1379

USBx_ERRSTAT field descriptions (continued)
Field Description
3
DFN8
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data
fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
2
CRC16
This bit is set when a data packet is rejected due to a CRC16 error.
1
CRC5EOF
This error interrupt has two functions. When the USB Module is operating in peripheral mode
(CTL[HOSTMODEEN]=0), this interrupt detects CRC5 errors in the token packets generated by the host.
If set the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (CTL[HOSTMODEEN]=1), this interrupt detects End Of
Frame (EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the
SOF counter reaches zero. This interrupt is useful when developing USB packet scheduling software to
ensure that no USB transactions cross the start of the next frame.
0
PIDERR
This bit is set when the PID check field fails.
51.4.12 Error Interrupt Enable register (USBx_ERREN)
Contains enable bits for each of the error interrupt sources within the USB module.
Setting any of these bits enables the respective interrupt source in ERRSTAT. Each bit is
set as soon as the error condition is detected. Therefore, the interrupt does not typically
correspond with the end of a token being processed. This register contains the value of
0x00 after a reset.
Address: 4005_5000h base + 8Ch offset = 4005_508Ch
Bit 7 6 5 4 3 2 1 0
Read
BTSERREN
OWNERRE
N
DMAERREN BTOERREN DFN8EN CRC16EN
CRC5EOFE
N
PIDERREN
Write
Reset 0 0 0 0 0 0 0 0
USBx_ERREN field descriptions
Field Description
7
BTSERREN
BTSERR Interrupt Enable
0 Disables the BTSERR interrupt.
1 Enables the BTSERR interrupt.
6
OWNERREN
OWNERR Interrupt Enable
This field is valid when the USB module is operating in peripheral mode (CTL[HOSTMODEEN]=0).
0 Disables the OWNERR interrupt.
1 Enables the OWNERR interrupt.
5
DMAERREN
DMAERR Interrupt Enable
0 Disables the DMAERR interrupt.
1 Enables the DMAERR interrupt.
Table continues on the next page...
Memory map/Register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
1316 NXP Semiconductors