NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1148 / 1379

Table 46-2. Mode, Edge, and Level Selection (continued)
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
10 Capture on Falling
Edge Only
11 Capture on Rising or
Falling Edge
01 01 Output compare Toggle Output on
match
10 Clear Output on match
11 Set Output on match
10 10 Edge-aligned PWM High-true pulses (clear
Output on match, set
Output on reload)
X1 Low-true pulses (set
Output on match, clear
Output on reload)
11 10 Output compare Pulse Output low on
match
01 Pulse Output high on
match
1 10 10 Center-aligned PWM High-true pulses (clear
Output on match-up,
set Output on match-
down)
01 Low-true pulses (set
Output on match-up,
clear Output on match-
down)
Address: Base a 20h (8d × i), where i=0d to 5d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 CHF
CHIE MSB MSA ELSB ELSA
0
DMA
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_CnSC field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
CHF
Channel Flag
Table continues on the next page...
Memory Map and Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1148 NXP Semiconductors