NXP Semiconductors K32 L2A Series, Reference Manual, Page: 125 / 1379

6.2.2.1 External pin reset (RESET_b)
This pin is open drain and has an internal pullup device. Asserting RESET_b wakes the
device from any mode.
The RESET_b pin can be disabled by programming RESET_PIN_CFG option bit to 0.
When this option is selected, there could be a short period of contention during a POR
ramp where the device drives the pin-out low prior to establishing the setting of this
option and releasing the reset function on the pin. When the RESET pin is disabled and
configured as a GPIO output, it operates as a pseudo open drain output.
6.2.2.1.1 RESET pin filter
The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. RCM_RPC[RSTFLTSS], RCM_RPC[RSTFLTSRW], and
RCM_RPC[RSTFLTSEL] control this functionality; see the
RCM chapter. The filters are
asynchronously reset by Chip POR. The reset value for each filter assumes the RESET
pin is negated.
For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, VLLS2
and VLLS1), the only filtering option is the LPO-based digital filter. The filtering logic
either switches to bypass operation or has continued filtering operation depending on the
filtering mode selected. When entering VLLS0, the RESET pin filter is disabled and
bypassed.
The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there
is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a
transition from low to high or high to low.
6.2.2.2 Low-voltage detect (LVD)
The chip includes a system for managing low-voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip
voltage. The LVD system is always enabled in Normal Run, Wait, or Stop mode. The
LVD system is disabled when entering VLPx, LLS, or VLLSx modes.
The LVD can be configured to generate a reset upon detection of a low-voltage condition
by setting PMC_LVDSC1[LVDRE] to 1. The low-voltage detection threshold is
determined by PMC_LVDSC1[LVDV]. After an LVD reset has occurred, the LVD
system holds the MCU in reset until the supply voltage has risen above the low voltage
detection threshold. RCM_SRS[LVD] is set following either an LVD reset or POR.
Chapter 6 Reset and Boot
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 125