NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1317 / 1379

USBx_ERREN field descriptions (continued)
Field Description
4
BTOERREN
BTOERR Interrupt Enable
0 Disables the BTOERR interrupt.
1 Enables the BTOERR interrupt.
3
DFN8EN
DFN8 Interrupt Enable
0 Disables the DFN8 interrupt.
1 Enables the DFN8 interrupt.
2
CRC16EN
CRC16 Interrupt Enable
0 Disables the CRC16 interrupt.
1 Enables the CRC16 interrupt.
1
CRC5EOFEN
CRC5/EOF Interrupt Enable
0 Disables the CRC5/EOF interrupt.
1 Enables the CRC5/EOF interrupt.
0
PIDERREN
PIDERR Interrupt Enable
0 Disables the PIDERR interrupt.
1 Enters the PIDERR interrupt.
51.4.13 Status register (USBx_STAT)
Reports the transaction status within the USB module. When the processor's interrupt
controller has received a TOKDNE, interrupt the Status Register must be read to
determine the status of the previous endpoint communication. The data in the status
register is valid when TOKDNE interrupt is asserted. The Status register is actually a
read window into a status FIFO maintained by the USB module. When the USB module
uses a BD, it updates the Status register. If another USB transaction is performed before
the TOKDNE interrupt is serviced, the USB module stores the status of the next
transaction in the STAT FIFO. Thus STAT is actually a four byte FIFO that allows the
processor core to process one transaction while the SIE is processing the next transaction.
Clearing the TOKDNE bit in the ISTAT register causes the SIE to update STAT with the
contents of the next STAT value. If the data in the STAT holding register is valid, the
SIE immediately reasserts to TOKDNE interrupt.
Address: 4005_5000h base + 90h offset = 4005_5090h
Bit 7 6 5 4 3 2 1 0
Read ENDP TX ODD 0
Write
Reset 0 0 0 0 0 0 0 0
Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1317