NXP Semiconductors K32 L2A Series, Reference Manual, Page: 594 / 1379

23.1.2 Features
Interface features between the device and the flash memory include:
• 8-bit, 16-bit, and 32-bit read operations to program flash memory.
• Read accesses to consecutive 32-bit spaces in memory that do not hit speculation
buffer or cache return the 2nd read data with no wait states.
• Crossbar master access protection for setting no access, read-only access, write-only
access, or read/write access for each crossbar master.
• 64-bit prefetch speculation buffer with controls for instruction/data access per master
• Invalidation control for the speculation buffer
• 128 bytes = 4-way by 4-set by 64 bits per entry cache, with controls for caching
instructions and/or data
• Enable and invalidation controls for cache
• Read accesses that hit a valid speculation or cache entry return the read data with no
wait states
23.2 Modes of operation
The FMC only operates when a bus master accesses the flash memory.
In terms of device power modes, the FMC only operates in run and wait modes, including
VLPR and VLPW modes.
For any device power mode where the flash memory cannot be accessed, the FMC is
disabled.
23.3 External signal description
The FMC has no external signals.
23.4 Memory map and register descriptions
In this device, the PFC = Platform Flash Controller does not have any program model;
therefore, there are no register definitions in the PFC chapter. All PFC operating controls
are in the Platform Control Register (MCMx_PLACR) in the MCM module.
Modes of operation
K32 L2A Reference Manual, Rev. 2, 01/2020
594 NXP Semiconductors