NXP Semiconductors K32 L2A Series, Reference Manual, Page: 339 / 1379

uses the source values from registers CA0 and CA1 for the key addition operation. The
KSx field specifies the shift for the key schedule operation to update the values in CA0
and CA1. The following table defines the specific shift function performed based on the
KSx field.
Table 15-6. Key shift function codes
KSx code KSx define Shift function
0 KSL1 Left 1
1 KSL2 Left 2
2 KSR1 Right 1
3 KSR2 Right 2
15.6.3.18 DES Key setup (DESK)
The DESK command performs the initial key transformation, permuted choice 1, defined
by the DES algorithm on CA0 and CA1 with CA0 containing bits 1–32 of the key and
CA1 containing bits 33–64 of the key
1
. If the DC bit is set, no shift operation performs
and the values C
0
and D
0
store back to CA0 and CA1, respectively. The DC bit must be
set for decrypt operations. If the DC bit is not set, a left shift by one also occurs and the
values C
1
and D
1
store back to CA0 and CA1, respectively. The DC bit should be cleared
for encrypt operations. If the CP bit is set and a key parity error is detected, CASR[DPE]
bit is set; otherwise, it is cleared.
15.6.3.19 Hash Function (HASH)
The HASH command performs a hashing operation on a set of registers and adds that
result to the value in CAA and stores the result in CAA. The specific hash function
performed is based on the HFx field as defined in the table below.
This table uses the following terms:
• ROTR
n
(CAx): rotate CAx register right n times
• SHR
n
(CAx): shift CAx register right n times
Table 15-7. Hash Function codes
HFx code HFx define Hash Function Hash logic
0 HFF MD5 F() (CA1 & CA2) | (CA1 & CA3)
1 HFG MD5 G() (CA1 & CA3) | (CA2 & CA3)
Table continues on the next page...
1. The DES algorithm numbers the most significant bit of a block as bit 1 and the least significant as bit 64.
Chapter 15 Cryptographic Acceleration Unit (CAU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 339