NXP Semiconductors K32 L2A Series, Reference Manual, Page: 838 / 1379

bit. This action queues an idle character to be sent as soon as the shifter is available. As
long as the character in the shifter does not finish while LPUART_CTRL[TE] is cleared,
the LPUART transmitter never actually releases control of the LPUART_TX pin.
An idle character can also be transmitted by writing to the LPUART_DATA register with
bit 13 set and the data bits also set. This supports transmitting the idle character as part of
the normal data stream and also allows the DMA to transmit a break character.
The length of the break character is affected by the LPUART_STAT[BRK13],
LPUART_CTRL[M], LPUART_BAUD[M10] and LPUART_BAUD[SNBS] bits as
shown below.
Table 31-1. Break character length
BRK13 M M10 SBNS Break character
length
0 0 0 0 10 bit times
0 0 0 1 11 bit times
0 1 0 0 11 bit times
0 1 0 1 12 bit times
0 X 1 0 12 bit times
0 X 1 1 13 bit times
1 0 0 0 13 bit times
1 0 0 1 13 bit times
1 1 0 0 14 bit times
1 1 0 1 14 bit times
1 X 1 0 15 bit times
1 X 1 1 15 bit times
31.3.2.2 Hardware flow control
The transmitter supports hardware flow control by gating the transmission with the value
of CTS. If the clear-to-send operation is enabled, the character is transmitted when CTS
is asserted. If CTS is deasserted in the middle of a transmission with characters remaining
in the receiver data buffer, the character in the shift register is sent and LPUART_TX
remains in the mark state until CTS is reasserted.
If the clear-to-send operation is disabled, the transmitter ignores the state of CTS.
The transmitter's CTS signal can also be enabled even if the same LPUART receiver's
RTS signal is disabled.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
838 NXP Semiconductors