NXP Semiconductors K32 L2A Series, Reference Manual, Page: 331 / 1379

CAU Base A 0x1000
CAU Base A 0x17FF
Direct loads
(commands only)
CNOP, ADRA, MVRA, MVAR, AESS, AESIS,
AESR, AESIR, DESR, DESK, HASH, SHS,
MDS, SHS2, and ILL commands
CAU Base A 0x0040
Reserved
(terminated with error)
CAU Base A 0x1FFF
CAU Base A 0x1800
Indirect load/stores
(commands & operands)
CAU Base A 0x1880
CAU Base A 0x18A8
CAU Base A 0x1840
CAU Base A 0x1868
CAU Base A 0x1900
CAU Base A 0x1928
CAU Base A 0x18C0
CAU Base A 0x18E8
CAU Base A 0x1980
CAU Base A 0x19A8
CAU Base A 0x19C0
CAU Base A 0x19E8
CAU Base A 0x1B00
CAU Base A 0x1B28
CAU Base A 0x1B40
CAU Base A 0x1B68
STR CAx
LDR CAx
RADR CAx
ADR CAx
ROTL CAx
XOR CAx
AESIC CAx
AESC CAx
Reserved
(terminated with illegal command)
Figure 15-3. CAU memory map
15.6.1.1 Direct loads
The CAU supports writing multiple commands in each 32-bit direct write operation. Each
9-bit opcode also includes a valid bit. Therefore, one, two, or three commands can be
transmitted in a single 32-bit PPB write. The following figure illustrates the accepted
formats for the 32-bit CAU write data value:
1 CAU_CMD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0
4
8
12
16 20
24
28
1 command
CAU_CMD1
1 0
CAU_CMD2
1 0 0 0 0 0 0 0 0 0 0 0
31 0 4 8 12 16 20 24 28
2 commands
CAU_CMD1 1 0 CAU_CMD2 1 0 1 CAU_CMD3
31 0 4 8 12 16 20 24 28
3 commands
Figure 15-4. Direct loads
Chapter 15 Cryptographic Acceleration Unit (CAU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 331