NXP Semiconductors K32 L2A Series, Reference Manual, Page: 326 / 1379

• Implement the innermost security kernel functions using the coprocessor instructions.
• Implement higher level functions in software by using the standard processor
instructions.
This partitioning of functions is key to minimizing size of the CAU while maintaining a
high level of throughput. Using software for some functions also simplifies the CAU
design. The CAU implements a set of coprocessor commands that operate on a register
file of 32-bit registers.
15.4 Features
The CAU includes the following distinctive features:
• Supports DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms
• Simple, flexible programming model
• Ability to send up to three commands in one data write operation
15.5 Memory map/Register definition
The CAU contains multiple registers used by each of the supported algorithms. The
following table shows registers that are applicable to each supported algorithm and
indicates the corresponding letter designations for each algorithm.
For more information on these letter designations, see the supported algorithm
specifications.
Code Register DES AES MD5 SHA-1 SHA-256
0 CAU Status
Register
(CASR) — — — — —
1 CAU
Accumulator
(CAA) — — a T T
2 General-
Purpose
Register 0
(CA0) C W0 — A A
3 General-
Purpose
Register 1
(CA1) D W1 b B B
Table continues on the next page...
Features
K32 L2A Reference Manual, Rev. 2, 01/2020
326 NXP Semiconductors