NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1180 / 1379

• If the selected mode is EPWM then CnV register is updated after CnV register was
written and the TPM counter changes from MOD to zero.
• If the selected mode is CPWM then CnV register is updated after CnV register was
written and the TPM counter changes from MOD to (MOD – 1).
46.4.14 DMA
The channel and overflow flags generate a DMA transfer request according to DMA and
CHnIE/TOIE bits.
See the following table for more information.
Table 46-3. DMA Transfer Request
DMA
CHnIE/
TOIE
Channel/Overflow DMA Transfer Request Channel/Overflow Interrupt
0 0 The channel/overflow DMA transfer request is
not generated. The channel/overflow interrupt is not generated.
0 1 The channel/overflow DMA transfer request is
not generated. The channel/overflow interrupt is generated if
(CHnF/TOF = 1).
1 0 The channel/overflow DMA transfer request is
generated if (CHnF/TOF = 1). The channel/overflow interrupt is not generated.
1 1 The channel/overflow DMA transfer request is
generated if (CHnF/TOF = 1). The channel/overflow interrupt is generated if
(CHnF/TOF = 1).
If DMA = 1, the CHnF/TOF bit can be cleared either by DMA transfer done or writing a
one to CHnF/TOF bit (see the following table).
Table 46-4. Clear CHnF/TOF Bit
DMA How CHnF/TOF Bit Can Be Cleared
0 CHnF/TOF bit is cleared by writing a 1 to CHnF/TOF bit.
1 CHnF/TOF bit is cleared either when the DMA transfer is done or by writing a 1 to CHnF/TOF bit.
46.4.15 Output triggers
The TPM generates output triggers for the counter and each channel that can be used to
trigger events in other peripherals.
The counter trigger asserts whenever the TOF is set and remains asserted until the next
increment.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1180 NXP Semiconductors