NXP Semiconductors K32 L2A Series, Reference Manual, Page: 325 / 1379

ALU
CAx
CA0-CA3
Operand1
Decode
Command
Hash
Go
AES Row
Datapath
Control
Result
Register
File
DES /
CAA
Figure 15-2. Top-level CAU block diagram
15.3 Overview
As the name suggests, the CAU provides a mechanism for memory-mapped register
reads and writes to be transformed into specific commands and operands sent to the CAU
coprocessor.
The CAU translator module performs the following functions:
• All the required functions affecting the transmission of commands to the CAU
module.
• If needed, stalling the PPB transactions based on the state of the 4-entry command/
data FIFO.
• Some basic integrity checks on PPB operations.
The set of implemented algorithms provides excellent support for network security
standards, such as SSL and IPsec. Additionally, using the CAU efficiently permits the
implementation of any higher level functions or modes of operation, such as HMAC,
CBC, and so on based on the supported algorithms.
The cryptographic algorithms are implemented partially in software with only functions
critical to increasing performance implemented in hardware. The CAU allows for
efficient, fine-grained partitioning of functions between hardware and software:
Chapter 15 Cryptographic Acceleration Unit (CAU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 325