NXP Semiconductors K32 L2A Series, Reference Manual, Page: 107 / 1379

Chapter 5
Clock Distribution
5.1 Introduction
This chapter provides an overview of the clock architecture: clock usage, clock
multiplexing, and clock gating.
The heart of the clocking architecture is the System Clock Generator (SCG) module. The
SCG controls four clock sources that can then be distributed to the main core platform,
the memory modules and the peripherals. The peripherals in general have two clocks, one
being the peripheral interface clock which is used by the core/DMA to interface with the
peripheral’s registers, the second being the peripheral functional clock which is used for
the main timing function of the peripheral (e.g. sources the baud rate for a serial
communications peripheral, or is the input clock to the counter of a timer peripheral).
The peripheral interface clock generally comes directly from the SCG to the peripheral.
The second peripheral functional clock is selected via the Peripheral Clock Control
(PCC) module. The SCG provides additional peripheral functional clocks with optional
dividers via the PCC module
The following diagram shows the various clock sources and clock trees for K32 L2A.
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 107