NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1329 / 1379

51.4.28 Frame Adjust Register (USBx_USBFRMADJUST)
Address: 4005_5000h base + 114h offset = 4005_5114h
Bit 7 6 5 4 3 2 1 0
Read
ADJ
Write
Reset 0 0 0 0 0 0 0 0
USBx_USBFRMADJUST field descriptions
Field Description
ADJ Frame Adjustment
In Host mode, the frame adjustment is a twos complement number that adjusts the period of each USB
frame in 12-MHz clock periods. A SOF is normally generated every 12,000 12-MHz clock cycles. The
Frame Adjust Register can adjust this by -128 to +127 to compensate for inaccuracies in the USB 48-MHz
clock. Changes to the ADJ bit take effect at the start of the next frame.
51.4.29 Miscellaneous Control register (USBx_MISCCTRL)
Address: 4005_5000h base + 12Ch offset = 4005_512Ch
Bit 7 6 5 4
Read 0
VFEDG_EN
Write
Reset 0 0 0 0
Bit
3 2 1 0
Read
VREDG_EN OWNERRISODIS SOFBUSSET SOFDYNTHLD
Write
Reset
0 0 0 0
USBx_MISCCTRL field descriptions
Field Description
7–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
VFEDG_EN
VREGIN Falling Edge Interrupt Enable
0 VREGIN falling edge interrupt disabled.
1 VREGIN falling edge interrupt enabled.
3
VREDG_EN
VREGIN Rising Edge Interrupt Enable
0 VREGIN rising edge interrupt disabled.
1 VREGIN rising edge interrupt enabled.
2
OWNERRISODIS
OWN Error Detect for ISO IN / ISO OUT Disable
This field is only valid for Peripheral mode, that is, CTL[HOSTMODEEN]=0.
Table continues on the next page...
Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1329