NXP Semiconductors K32 L2A Series, Reference Manual, Page: 53 / 1379

Core Modules
3.4.1 Introduction
This device has one Arm Cortex M0+ CPU, called the Core.
• The enhanced Arm Cortex M0+ is the member of the Cortex-M Series of processors,
with microcontroller cores focused on very cost sensitive, low power applications.
• Has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component.
• Has hardware debug functionality, including support for simple program trace
capability.
• The processor supports the Armv6-M instruction set (Thumb) architecture, including
all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions.
• Upward compatible with other Cortex-M profile processors.
3.4.2 Arm Cortex M0+ core
Arm Cortex M0+ parameter settings are:
Table 3-3. Arm Cortex-M0+ parameter settings
Parameter Verilog name Value Description
Arch Clock Gating ACG 1 = Present Implements architectural clock gating
DAP Slave Port Support AHBSLV 1 Supports any AHB debug access port (like the
CM0+ DAP)
DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM table
Endianess BE 0 Little endian control for data transfers
Breakpoints BKPT 2 Implements 2 breakpoints
Debug Support DBG 1 = Present —
Halt Event Support HALTEV 1 = Present —
I/O Port IOP 1 = Present Implements single-cycle ld/st accesses to
special address space
IRQ Mask Enable IRQDIS 0x00000000 All 32 IRQs are used (set if IRQ is disabled)
Debug Port Protocol JTAGnSW 0 = SWD SWD protocol, not JTAG
Core Memory Protection MPU 1 = Present Includes Arm based MPU with 8 regions
implemented.
1
Number of IRQs NUMIRQ 32 Full NVIC request vector
Reset all registers RAR 0 = Standard Do not force all registers to be async reset
Multiplier SMUL 0 = Fast Mul Implements single-cycle multiplier
Multi-drop Support SWMD 0 = Absent Do not include serial wire support for multi-
drop
Table continues on the next page...
3.4
Chapter 3 Chip Configuration
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 53