NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1173 / 1379

If the selected edge by channel (n) bits is detected at channel (n) input, then CH(n)F bit is
set and the channel (n) interrupt is generated (if CH(n)IE = 1). If the selected edge by
channel (n+1) bits is detected at channel (n) input, then CH(n+1)F bit is set and the
channel (n+1) interrupt is generated (if CH(n+1)IE = 1).
The C(n)V register stores the value of TPM counter when the selected edge by channel
(n) is detected at channel (n) input. The C(n+1)V register stores the value of TPM
counter when the selected edge by channel (n+1) is detected at channel (n) input.
Note
• The CH(n)F, CH(n)IE, MS(n)A, ELS(n)B, and ELS(n)A
bits are channel (n) bits.
• The CH(n+1)F, CH(n+1)IE, MS(n+1)A, ELS(n+1)B, and
ELS(n+1)A bits are channel (n+1) bits.
• The Combine Input Capture mode must be used with
ELS(n)B:ELS(n)A = 0:1 or 1:0, ELS(n+1)B:ELS(n+1)A =
0:1 or 1:0.
46.4.10 Input Capture Filter
The input capture filter function is only in input capture mode, or in software compare
mode when quadrature decoder mode is enabled.
First, the input signal is synchronized by the counter clock. Following synchronization,
the input signal enters the filter block. See the following figure.
counter clock
filter counter Logic to define
the filter output
filter output
divided by 4
channel (n) input after
the synchronizer
Logic to control
the filter counter
CHnFVAL[3:0]
C
S
Q
CLK
Figure 46-23. Channel input filter
When there is a state change in the input signal, the counter is reset and starts counting
up. As long as the new state is stable on the input, the counter continues to increment.
When the counter is equal to (CHnFVAL[3:0] × 4), the state change of the input signal is
validated.
Chapter 46 Timer/PWM Module (TPM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1173