NXP Semiconductors K32 L2A Series, Reference Manual, Page: 529 / 1379

• Set ANACK bit in the CTRL register to enable NACK generation. The ISO 7816-3
spec allows the EMV SIM module to NACK any communication errors that occur
during the initial communication at 12 ETU.
NOTE
The Europay MasterCard and VISA (EMV) cards are
similar to “T=1”, but do not allow the EMV SIM module to
NACK during the initial communication
• Enable RDTF and RFO interrupts by setting RDT_IM and RFO_IM bits in
INT_MASK register. These interrupts are enabled to notify the software when
characters are received. A threshold can be set for the number of characters to
receive before generating an interrupt.
• Set desired threshold for received characters by writing RDT in RX_THD register
The EMV SIM should be setup to perform in initial character mode during ATR
detection. This will cause the hardware to identify the first valid character sent during the
ATR as an initial character. This character will automatically configure the hardware for
the data convention used by the Smart Card.
• Set Initial Character Mode by setting the ICM bit in the CTRL register
The ISO 7816-3 spec requires that Smart Cards meet certain timing restrictions. One of
these is the time from the de-assertion of the card reset to the beginning of the ATR
sequence. The EMV SIM module's General Purpose Counter can be used to verify that
the Smart Card begins its ATR within the 400 to 40,000 card clock cycle range.
• Set the General Purpose Counter 0 or 1 Timeout Value to 0x9C40 using
GPCNT0/1_VAL register.
• Enable General Purpose Counter Interrupt by clearing GPCNT0/1_IM in
INT_MASK register.
• Enable General Purpose Counter by programming the GPCNT0/1_CLKSEL[1:0] bits
to 01, so that the card clock is used for counting.
The ISO7816-3 spec states that the maximum allowed time between two characters
during the ATR is 9600 ETUs (Initial Waiting Time). The Character Wait Time Counter
should be setup to detect any errors for this condition.
• Set Character Wait Time Counter Comparator to 9600 using the CWT_VAL register
• Enable the Character Wait Time Counter Interrupt by clearing CWT_ERR_IM in
INT_MASK register
• Enable the Character Wait Time Counter by setting the CWT_EN bit in the CTRL
register
The last step in preparing for ATR reception is to enable the receiver.
• Set RCV_EN bit in CTRL register
Chapter 21 Smart Card Interface Module (EMV SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 529