NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1179 / 1379

channel 0
channel 1
TPM counter
increment/decrement
TPM counter
MOD
0x0000
Time
set TOF
clear TOFDIR
-1
set TOF
clear TOFDIR
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1
-1 -1
Figure 46-31. TPM counter overflow in down counting for Quadrature Decoder mode
46.4.13 Registers Updated from Write Buffers
46.4.13.1 MOD Register Update
If (CMOD[1:0] = 0:0) then MOD register is updated when MOD register is written.
If (CMOD[1:0] ≠ 0:0), then MOD register is updated according to the CPWMS bit, that
is:
• If the selected mode is not CPWM then MOD register is updated after MOD register
was written and the TPM counter changes from MOD to zero.
• If the selected mode is CPWM then MOD register is updated after MOD register was
written and the TPM counter changes from MOD to (MOD – 1).
46.4.13.2 CnV Register Update
If (CMOD[1:0] = 0:0) then CnV register is updated when CnV register is written.
If (CMOD[1:0] ≠ 0:0), then CnV register is updated according to the selected mode, that
is:
• If the selected mode is output compare then CnV register is updated on the next TPM
counter increment (end of the prescaler counting) after CnV register was written.
Chapter 46 Timer/PWM Module (TPM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1179