NXP Semiconductors K32 L2A Series, Reference Manual, Page: 388 / 1379

18.4.1 DAC Data Low Register (DACx_DATnL)
Address: 4006_A000h base + 0h (2d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read
DATA0
Write
Reset 0 0 0 0 0 0 0 0
DACx_DATnL field descriptions
Field Description
DATA0 DATA0
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula: V
out
= V
in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.
18.4.2 DAC Data High Register (DACx_DATnH)
Address: 4006_A000h base + 1h (2d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read 0
DATA1
Write
Reset 0 0 0 0 0 0 0 0
DACx_DATnH field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DATA1 DATA1
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. V
out
= V
in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
18.4.3 DAC Status Register (DACx_SR)
If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
request is done. Writing 0 to a field clears it whereas writing 1 has no effect. After reset,
DACBFRPTF is set and can be cleared by software, if needed. The flags are set only
when the data buffer status is changed.
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
388 NXP Semiconductors