NXP Semiconductors K32 L2A Series, Reference Manual, Page: 160 / 1379

NOTE
• A pull-up resistor (typically 4.7 KΩ) must be connected to
the EMVSIM0_IO pin if this pin is configured as EMV
SIM function.
• PTB0/1, PTC3/4, PTD4/5/6/7 have both high drive and
normal/low drive capability. PTD4, PTD5, PTD6, PTD7,
PTE20, PTE21, PTE22, PTE23 are also fast pins. When a
high bit rate is required on the communication interface
pins, it is recommended to use fast pins. In case of high bus
loading, the high drive strength of high drive pins must be
enabled by setting the corresponding PORTx_PCRn[DSE]
bit.
• RESET_b pin is open drain with internal pullup device and
passive analog filter when configured as RESET pin
(default state after POR). When this pin is configured to
other shared functions, the passive analog filter is disabled.
• NMI0_b pin has pullup device enabled and passive analog
filter disabled after POR.
• SWD_DIO pin has pullup device enabled after POR.
SWD_CLK has pulldown device enabled after POR.
100
LQFP
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
1 1 PTE0 ADC0_SE16 ADC0_SE16 PTE0/
RTC_CLKOUT LPSPI1_SIN LPUART1_TX CMP0_OUT LPI2C1_SDA
2 2 PTE1/
LLWU_P0 ADC0_SE17 ADC0_SE17 PTE1/
LLWU_P0 LPSPI1_SOUT LPUART1_RX LPI2C1_SCL
3 — PTE2/
LLWU_P1 ADC0_SE18 ADC0_SE18 PTE2/
LLWU_P1 LPSPI1_SCK LPUART1_
CTS_b LPI2C1_SDAS
4 — PTE3 ADC0_SE19 ADC0_SE19 PTE3 LPSPI1_SIN LPUART1_
RTS_b LPI2C1_SCLS
5 — PTE4/
LLWU_P2 DISABLED PTE4/
LLWU_P2 LPSPI1_PCS0
6 — PTE5 DISABLED PTE5 LPSPI1_PCS1
7 — PTE6/
LLWU_P16 DISABLED PTE6/
LLWU_P16 LPSPI1_PCS2 USB_SOF_
OUT
8 3 VDD VDD VDD
9 4 VSS VSS VSS
10 5 USB0_DP USB0_DP USB0_DP
11 6 USB0_DM USB0_DM USB0_DM
12 7 VOUT33 VOUT33 VOUT33
13 8 VREGIN VREGIN VREGIN
14 — PTE16 ADC0_DP1/
ADC0_SE1 ADC0_DP1/
ADC0_SE1 PTE16 LPSPI0_PCS0 LPUART2_TX TPM0_CLKIN LPSPI1_PCS3 FXIO0_D0
Pinout
K32 L2A Reference Manual, Rev. 2, 01/2020
160 NXP Semiconductors