NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1126 / 1379

• Wait
• Very-Low Power Wait (VLPW)
44.4.4.1 WAIT mode
WAIT mode is entered when the Arm core enters the Sleep-Now or Sleep-On-Exit modes
while SLEEPDEEP is cleared. The Arm CPU enters a low-power state in which it is not
clocked, but peripherals continue to be clocked provided they are enabled.
When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in
RUN mode, beginning with the stacking operations leading to the interrupt service
routine.
A system reset causes an exit from WAIT mode, returning the device to normal RUN
mode.
A system reset causes an exit from WAIT mode, temporarily returning the device to
RUN mode before transitioning into VLPR during the device reset flow.
44.4.4.2 Very-Low-Power Wait (VLPW) mode
VLPW mode is entered by entering the Sleep-Now or Sleep-On-Exit mode while
SLEEPDEEP is cleared and the device is in VLPR mode.
In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state,
the regulator is designed to supply enough current to the device at a reduced frequency.
To further reduce power in this mode, disable the clocks to unused modules.
VLPR mode restrictions also apply to VLPW.
When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the
interrupt service routine.
A system reset causes an exit from VLPW mode, returning the device to normal RUN
mode.
A system reset causes an exit from VLPW mode, temporarily returning the device to
RUN mode before transitioning into VLPR during the device reset flow.
44.4.5 Stop modes
This device contains a variety of stop modes to meet your application needs.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1126 NXP Semiconductors