NXP Semiconductors K32 L2A Series, Reference Manual, Page: 507 / 1379

21.5.13 Transmit Data Buffer (EMVSIMx_TX_BUF)
Address: 4004_E000h base + 30h offset = 4004_E030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
TX_BYTE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EMVSIMx_TX_BUF field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
TX_BYTE Transmit Data Byte
Write to this register to fill the transmit FIFO with the bytes to be transmitted. The Tx FIFO can be written
to only when the transmitter is enabled. Writing to this register while transmitter is disabled will lead to
ignoring of all write accesses to this register. Reads to this register will return zeros.
NOTE: Writing more data to the transmit FIFO than it can hold, will cause a Transmit FIFO Full (TFF)
error.
21.5.14 Transmitter Guard ETU Value Register (EMVSIMx_TX_GETU)
Address: 4004_E000h base + 34h offset = 4004_E034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
GETU
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EMVSIMx_TX_GETU field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
GETU Transmitter Guard Time Value in ETU
Used to control the number of additional Elementary Time Units (ETUs) inserted between bytes
transmitted by the EMV SIM transmitter. An ETU is equivalent to one bit time at the given baud rate (for
example, the length of a START bit). The guard time has no effect on the EMV SIM receiver. A value of
0x00 inserts no additional ETUs, while a value of 0xFE inserts 254 additional ETUs. A value of 0xFF
subtracts one ETU by reducing the number of STOP bits from two to one.
0 no additional ETUs inserted (default)
1 1 additional ETU inserted
...
Table continues on the next page...
Chapter 21 Smart Card Interface Module (EMV SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 507