NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1075 / 1379

SCG_SIRCCSR field descriptions
Field Description
31–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25
SIRCSEL
Slow IRC Selected
0 Slow IRC is not the system clock source
1 Slow IRC is the system clock source
24
SIRCVLD
Slow IRC Valid
0 Slow IRC is not enabled or clock is not valid
1 Slow IRC is enabled and output clock is valid
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–4
Reserved
This field is reserved and is always has the value 0
This field is reserved.
3
Reserved
This field is reserved and is always has the value 0
This field is reserved.
This read-only field is reserved and always has the value 0.
2
SIRCLPEN
Slow IRC Low Power Enable
0 Slow IRC is disabled in VLP modes
1 Slow IRC is enabled in VLP modes
1
SIRCSTEN
Slow IRC Stop Enable
0 Slow IRC is disabled in supported Stop modes
1 Slow IRC is enabled in supported Stop modes
0
SIRCEN
Slow IRC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 Slow IRC is disabled
1 Slow IRC is enabled
42.2.12 Slow IRC Divide Register (SCG_SIRCDIV)
To prevent glitches to the output divided clock, change SIRDIV when the Slow IRC is
disabled.
Address: 4007_B000h base + 204h offset = 4007_B204h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 SIRCDIV
3
0 SIRCDIV
2
0 SIRCDIV
1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 42 System Clock Generator (SCG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1075