NXP Semiconductors K32 L2A Series, Reference Manual, Page: 76 / 1379

Table 3-18. Reference links to related information (continued)
Topic Related module Reference
System memory map — System memory map
Clocking — Clock distribution
Power management — Power management
Signal multiplexing Port control Signal multiplexing
3.8.1.1 TPM instantiation information
This device contains 3 low-power Timer/PWM modules (TPM), which can all be
functional in Stop/VLPS mode. In Stop/VLPS mode, the clock source is either external or
internal. The following table shows how these modules are configured.
Table 3-19. TPM configuration
TPM instance Number of channels Features/usage
TPM0 6 Basic TPM, support for input filters, dead-time insertion and
quadrature decode, functional in Stop/VLPS mode
TPM1 2 Basic TPM, support for input filters, dead-time insertion and
quadrature decode, functional in Stop/VLPS mode
TPM2 2 Basic TPM, support for input filters, dead-time insertion and
quadrature decode, functional in Stop/VLPS mode
• TPM0 and TPM1 are accessed via the AIPS1 peripheral bridge.
• TPM2 is accessed via the AIPS0 peripheral bridge.
• TPM0 and TPM2 can be optionally clocked from the TPM1 clock, thereby providing
synchronization for all 3 timers.
3.8.1.2 Clock options
Each TPM module has its own TPM clock. The selected source is controlled by a PCC
module.
Each TPM also supports an external clock mode (TPMx_SC[CMOD]=1x) in which the
counter increments after a rising edge detect of an external clock input (synchronized to
the TPM clock source). The external clock can be either TPM0_CLKIN or
TPM1_CLKIN.
NOTE
The selected external clock must be less than half the frequency
of the TPM clock source.
Timers
K32 L2A Reference Manual, Rev. 2, 01/2020
76 NXP Semiconductors