NXP Semiconductors K32 L2A Series, Reference Manual, Page: 834 / 1379

LPUARTx_FIFO field descriptions (continued)
Field Description
110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
9
TXOFE
Transmit FIFO Overflow Interrupt Enable
When this field is set, the TXOF flag generates an interrupt to the host.
0 TXOF flag does not generate an interrupt to the host.
1 TXOF flag generates an interrupt to the host.
8
RXUFE
Receive FIFO Underflow Interrupt Enable
When this field is set, the RXUF flag generates an interrupt to the host.
0 RXUF flag does not generate an interrupt to the host.
1 RXUF flag generates an interrupt to the host.
7
TXFE
Transmit FIFO Enable
When this field is set, the built in FIFO structure for the transmit buffer is enabled. The size of the FIFO
structure is indicated by TXFIFOSIZE. If this field is not set, the transmit buffer operates as a FIFO of
depth one dataword regardless of the value in TXFIFOSIZE. Both CTRL[TE] and CTRL[RE] must be
cleared prior to changing this field.
0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
6–4
TXFIFOSIZE
Transmit FIFO. Buffer Depth
The maximum number of transmit datawords that can be stored in the transmit buffer. This field is read
only.
001 Transmit FIFO/Buffer depth = 4 datawords.
3
RXFE
Receive FIFO Enable
When this field is set, the built in FIFO structure for the receive buffer is enabled. The size of the FIFO
structure is indicated by the RXFIFOSIZE field. If this field is not set, the receive buffer operates as a FIFO
of depth one dataword regardless of the value in RXFIFOSIZE. Both CTRL[TE] and CTRL[RE] must be
cleared prior to changing this field.
0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
RXFIFOSIZE Receive FIFO. Buffer Depth
The maximum number of receive datawords that can be stored in the receive buffer before an overrun
occurs. This field is read only.
001 Receive FIFO/Buffer depth = 4 datawords.
Register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
834 NXP Semiconductors