NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1318 / 1379

USBx_STAT field descriptions
Field Description
7–4
ENDP
This four-bit field encodes the endpoint address that received or transmitted the previous token. This
allows the processor core to determine the BDT entry that was updated by the last USB transaction.
3
TX
Transmit Indicator
0 The most recent transaction was a receive operation.
1 The most recent transaction was a transmit operation.
2
ODD
This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
51.4.14 Control register (USBx_CTL)
Provides various control and configuration information for the USB module.
Address: 4005_5000h base + 94h offset = 4005_5094h
Bit 7 6 5 4
Read
JSTATE SE0
TXSUSPENDTOKENB
USY
RESET
Write
Reset 0 0 0 0
Bit 3 2 1 0
Read
HOSTMODEEN RESUME ODDRST USBENSOFEN
Write
Reset 0 0 0 0
USBx_CTL field descriptions
Field Description
7
JSTATE
Live USB differential receiver JSTATE signal
The polarity of this signal is affected by the current state of LSEN .
6
SE0
Live USB Single Ended Zero signal
5
TXSUSPENDTOKENBUSY
In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token.
Software must not write more token commands to the Token Register when TOKEN_BUSY is
set. Software should check this field before writing any tokens to the Token Register to ensure
that token commands are not lost.
In Device mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
reception. Clearing this bit allows the SIE to continue token processing. This bit is set by the
SIE when a SETUP Token is received allowing software to dequeue any pending packet
transactions in the BDT before resuming token processing.
4
RESET
Setting this bit enables the USB Module to generate USB reset signaling. This allows the USB
Module to reset USB peripherals. This control signal is only valid in Host mode
(CTL[HOSTMODEEN]=1). Software must set RESET to 1 for the required amount of time and
then clear it to 0 to end reset signaling.
Table continues on the next page...
Memory map/Register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
1318 NXP Semiconductors