NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1258 / 1379

48.1.3.3.37.1 Address
Register Offset
TRNG0_SEC_CFG 400A50A0h
48.1.3.3.37.2 Function
The TRNG0 Security Configuration Register is a read/write register used to control the
test mode, programmability and state modes of the TRNG0. Many bits are place holders
for this version. More configurability will be added here. Clears on asynchronous reset.
For TRNG0 releases before 2014/July/01, offsets 0xA0 to 0xAC used to be 0xB0 to
0xBC respectively. So, update newer tests that use these registers, if hard coded.
48.1.3.3.37.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
SK_V
AL
NO_P
RGM
SH0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
48.1.3.3.37.4 Fields
Field Function
31-3
—
Reserved.
2
SK_VAL
Reserved. DRNG-specific, not applicable to this version.
0 - See DRNG version.
1 - See DRNG version.
1
NO_PRGM
If set, the TRNG registers cannot be programmed. That is, regardless of the TRNG access mode in the
TRNG0 Miscellaneous Control Register.
0 - Programability of registers controlled only by the TRNG0 Miscellaneous Control Register's
access mode bit.
1 - Overides TRNG0 Miscellaneous Control Register access mode and prevents TRNG register
programming.
0
SH0
Reserved. DRNG specific, not applicable to this version.
0 - See DRNG version.
1 - See DRNG version.
Standalone True Random Number Generator (SA-TRNG).
K32 L2A Reference Manual, Rev. 2, 01/2020
1258 NXP Semiconductors