NXP Semiconductors K32 L2A Series, Reference Manual, Page: 736 / 1379

The timing parameters must be configured to meet the requirements of the I2C
specification, this will depend on the mode being supported, the frequency of the LPI2C
functional clock. Some example configurations are provided below.
Table 27-3. LPI2C Example Timing Configurations
I2C Mode Clock
Frequency
Baud Rate PRESCAL
ER
FILTSCL/
FILTSDA
SETHOLD CLKLO CLKHI DATAVD
Fast 8 MHz 400 kbps 0x0 0x0/0x0 0x04 0x0B 0x05 0x02
Fast+ 8 MHz 1 Mbps 0x0 0x0/0x0 0x02 0x03 0x01 0x01
Fast 48 MHz 400 kbps 0x2 0x1/0x1 0x07 0x11 0x0B 0x03
Fast+ 48 MHz 1 Mbps 0x2 0x1/0x1 0x03 0x06 0x04 0x04
Fast+ 48 MHz 1 Mbps 0x0 0x1/0x1 0x1D 0x18 0x13 0x0F
HS-mode 48 MHz 3.2 Mbps 0x0 0x0/0x0 0x07 0x08 0x03 0x01
Fast 60 MHz 400 kbps 0x1 0x2/0x2 0x11 0x28 0x21 0x08
Fast+ 60 MHz 1 Mbps 0x1 0x2/0x2 0x07 0x0F 0x0B 0x01
HS-mode 60 MHz 3.33 Mbps 0x1 0x0/0x0 0x04 0x03 0x04 0x01
Ultrafast 60 MHz 5 Mbps 0x0 0x0/0x0 0x02 0x05 0x03 0x01
The formula to calculate number of cycles per bit is as follows:
Baud rate divide = ((CLKLO+CLKHI+2)*2^PRESCALER) +
ROUNDDOWN((2+FILTSCL)/2^PRESCALER)
This assumes SCL will pull high within 1 cycle of the LPI2C functional clock, this will
depend on the pullup resistor and loading on the SCL pin.
27.3.2.5 Error Conditions
The LPI2C master will monitor for errors while it is active, the following conditions will
generate an error flag and block a new START condition from being sent until the flag is
cleared by software:
• START or STOP condition detected and not generated by LPI2C master (sets
MSR[ALF]).
• Transmitting data on SDA and different value being received (sets MSR[ALF]).
• NACK detected when transmitting data, provided MCFGR1[IGNACK] is clear (sets
MSR[NDF]).
• NACK detected and expecting ACK for address byte, provided MCFGR1[IGNACK]
is clear (sets MSR[NDF]).
• ACK detected and expecting NACK for address byte, provided MCFGR1[IGNACK]
is clear (sets MSR[NDF]).
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
736 NXP Semiconductors