NXP Semiconductors K32 L2A Series, Reference Manual, Page: 116 / 1379

Example Peripheral Clocking - USB
Registers
PCC_USB0FS
DIV1
DIV1
DIV1
DIV1
SOSC
SPLL
FIRC
SIRC
SCG
SCG DIVCORE
SPLLDIV1_CLK
SOSCDIV1_CLK
SIRCDIV1_CLK
FIRCDIV1_CLK
Registers
USB0
COUNTER
DIVCORE_CLK
Peripheral Interface Clock
Figure 5-3. Example Peripheral Clocking (USB)
5.7 Programming model
The selection and multiplexing of system clock sources is controlled and programmed via
the System Clock Generation (SCG) module. First, the SCG selects the clock source for
driving the main CPU and the peripheral interface clocks, DIVCORE_CLK and
DIVSLOW_CLK respectively.
The DIVCORE_CLK and the DIVSLOW_CLK clocks support three different modes of
operation, normal RUN mode, HSRUN mode and Low Power RUN mode. Each of these
run modes can have different clock sources and dividers options and are automatically
selected via the options provided in SCG_xCCR registers. Each specific run mode is
configured via the SMC_PMCTRL register.
Secondly the SCG can provide additional peripheral functional clocks to the various
peripherals, via 3 optional output clock trees from each of the four sources. Each of the
peripheral functional clock outputs has a programmable divider within the SCG. These
xxxx
DIVy_CLK outputs are fed to the PCC module where the peripheral can select one of
these alternative clock sources to clock the timing function of that peripheral.
Programming model
K32 L2A Reference Manual, Rev. 2, 01/2020
116 NXP Semiconductors