NXP Semiconductors K32 L2A Series, Reference Manual, Page: 574 / 1379

When configured for parallel shift, either 4, 8, 16 or 32-bits can be shifted on every Shift
clock. If an adjacent shifter is selected as the input source (SHIFTCFG[INSRC]=1), the
least significant 4, 8, 16 or 32-bits from the adjacent shifter will be sampled on each Shift
clock.
For shifters supporting parallel receive (SHIFTER3, SHIFTER7), the shifter can be
configured to sample multiple pins (SHIFTCFG[INSRC]=0), with PWIDTH and
PINSEL selecting the pins as follows: FXIO_D[PWIDTH]:FXIO_D[PINSEL].
Note that if PWIDTH is less than the number of bits being shifted on each Shift clock,
then the most significant bits will be masked with 0 e.g. if PINSEL=7 and PWIDTH=6,
then SHIFTER[31:24] will sample {0,0,FXIO_D[12:7]} on each Shift clock.
For shifters supporting parallel transmit (SHIFTER0, SHIFTER4), the shifter can be
configured to drive multiple pins using SHIFTCTL[PINCFG], with PWIDTH and
PINSEL selecting the pins as follows: FXIO_D[PWIDTH]:FXIO_D[PINSEL].
Note that if PWIDTH is less than the number of bits being shifted on each Shift clock,
then the most significant pins will not be driven e.g. if PINSEL=7 and PWIDTH=6, then
SHIFTER[5:0] will drive only FXIO_D[12:7] on each Shift clock.
When configuring a pin as an input (this includes a timer trigger configured as a pin
input), the input signal is first synchronized to the FlexIO clock before the signal is used
by a timer or shifter. This introduces a small latency of between 0.5 to 1.5 FlexIO clock
cycles when using an external pin input to generate an output or control a shifter. This
sets the maximum setup time at 1.5 FlexIO clock cycles.
If an input is used by more than one timer or shifter then the synchronization occurs once
to ensure any edge is seen on the same cycle by all timers and shifters using that input.
Note that FlexIO pins are also connected internally, configuring a FlexIO shifter or timer
to output data on an unused pin will make an internal connection that allows other
shifters and timer to use this pin as an input. This allows a shifter output to be used to
trigger a timer or a timer output to be shifted into a shifter. This path is also synchronized
to the FlexIO clock and therefore incurs a 1 cycle latency.
So when using a Pin input as a Timer Trigger, Timer Clock or Shifter Data Input, the
following synchronization delays occur:
1. 0.5 – 1.5 FlexIO clock cycles for external pin
2. 1 FlexIO clock cycle for an internally driven pin
For timing considerations such as output valid time and input setup time for specific
applications (SPI Master, SPI Slave, I2C Master, I2S Master, I2S Slave) please refer to
the FlexIO Application Information Section.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
574 NXP Semiconductors