NXP Semiconductors K32 L2A Series, Reference Manual, Page: 584 / 1379

enabling bit clock and frame sync generation. Data transfers can be supported using the
DMA controller and the shifter error flag will set on transmit underrun or receive
overflow.
The bit clock frequency is an even integer divide of the FlexIO clock frequency, and the
initial frame sync assertion occurs at the same time as the first bit clock edge. The timer
uses the start bit to ensure the frame sync is generated one clock cycle before the first
output data.
Due to synchronization delays, the setup time for the receiver input is 1.5 FlexIO clock
cycles, so the maximum baud rate is divide by 4 of the FlexIO clock frequency.
Table 22-12. I2S Master Configuration
Register Value Comments
SHIFTCFGn 0x0000_0001 Load transmit data on first shift and stop
bit disabled.
SHIFTCTLn 0x0003_0002 Configure transmit using Timer 0 on
rising edge of clock with output data on
Pin 0.
SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.
SHIFTCTL(n+1) 0x0080_0101 Configure receive using Timer 0 on
falling edge of clock with input data on
Pin 1.
TIMCMPn 0x0000_3F01 Configure 32-bit transfer with baud rate
of divide by 4 of the FlexIO clock. Set
TIMCMP[15:8] = (number of bits x 2) - 1.
Set TIMCMP[7:0] = (baud rate divider /
2) - 1.
TIMCFGn 0x0000_0202 Configure start bit, enable on trigger high
and never disable. Initial clock state is
logic 1.
TIMCTLn 0x01C3_0201 Configure dual 8-bit counter using Pin 2
output (bit clock), with Shifter 0 flag as
the inverted trigger. Set PINPOL to
invert the output shift clock.
TIMCMP(n+1) 0x0000_007F Configure 32-bit transfer with baud rate
of divide by 4 of the FlexIO clock. Set
TIMCMP[15:0] = (number of bits x baud
rate divider) - 1.
TIMCFG(n+1) 0x0000_0100 Enable when Timer 0 is enabled and
never disable.
TIMCTL(n+1) 0x0003_0383 Configure 16-bit counter using inverted
Pin 3 output (as frame sync).
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUFBIS, use the Shifter Status
Flag to indicate when data can be
written using interrupt or DMA request.
Can support LSB first transfer by writing
to SHIFTBUF register instead.
Table continues on the next page...
Application Information
K32 L2A Reference Manual, Rev. 2, 01/2020
584 NXP Semiconductors