NXP Semiconductors K32 L2A Series, Reference Manual, Page: 517 / 1379

initial character for inverse convention and will set the PEF
flag.
21.6.3.3 Receiver Diagnostics
The EMV SIM module performs diagnostic checks on the incoming messages. These
checks include parity check and message frame checks.
Parity Error Detection: The receiver is responsible for detecting parity errors in the
received data. Data is always transmitted with even parity, except when in inverse
convention mode. In inverse convention mode, all data bits and the parity bit are
complemented making the data appear to be odd parity. The parity bit is defined as the
10th bit of the received data. The parity of the 2nd through 10th received bits is
calculated by the receiver parity logic. This logic determines if the parity of the 9
received bits is correct.
When a parity error is detected on a given byte, the parity error flag (PEF bit) is asserted
in the RX_STATUS register if NACK generation on errors is disabled (ANACK = 0 in
CTRL register). The parity error flag does not generate an interrupt to the system,
however, the module can cause the transmitter to transmit a NACK (if ANACK = 1 in
CTRL register) without software needed to enable transmitter for this and request re-
transmission of the current byte.
Framing Error Detection: The receiver is responsible for detecting framing errors in the
received data. Data is always transmitted with 2 STOP bits, except when in 11 ETU
mode, where there is one STOP bit. The STOP bits are defined as high state at the 11th
and 12th bit positions in the received data. In either mode, the receiver expects to see a
high at the 11th bit position in the received data. If a low is detected at the 11th bit
position, the receiver indicates a framing error for that byte.
When a framing error is detected on a given byte, the FEF bit is set in the RX_STATUS
register. A framing error cannot cause an interrupt, nor can it create a NACK pulse to the
Smart Card asking for a retransmission of the corrupted data.
LRC & CRC: The receiver also checks the LRC or CRC on the incoming block of bytes
(if LRC or CRC is enabled). The result of the CRC or LRC check is updated in the
RX_STATUS register once the complete message block is received.
Chapter 21 Smart Card Interface Module (EMV SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 517