NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1120 / 1379

Table 44-2. Power mode transition triggers (continued)
Transition # From To Trigger conditions
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in Arm
core.
See note.
1
STOP RUN Interrupt or Reset
3 RUN VLPR The core, system, bus and flash clock frequencies and SCG
clocking mode are restricted in this mode. See the Power
Management chapter for the maximum allowable frequencies
and SCG modes supported.
Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.
NOTE: In order to limit peak current, PMPROT[AVLP] and
PMCTRL[RUNM] bits can be set on any Reset via
Flash IFR settings, causing the SMC to transition the
MCU from RUN->VLPR during the reset recovery
sequence.
VLPR RUN Set PMCTRL[RUNM]=00 or
Reset.
4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, which is controlled in System Control Register in Arm
core.
See note.
1
VLPW VLPR Interrupt
5 VLPW RUN Reset
6 VLPR VLPS PMCTRL[STOPM]=000
3
or 010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in Arm
core.
See note.
1
VLPS VLPR Interrupt
NOTE: If VLPS was entered directly from RUN (transition
#7), hardware forces exit back to RUN and does not
allow a transition to VLPR.
7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in Arm
core.
See note.
1
VLPS RUN Interrupt and VLPS mode was entered directly from RUN or
Reset
8 RUN VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit
modes entered with SLEEPDEEP set, which is controlled in
System Control Register in Arm core.
VLLSx RUN Wakeup from enabled LLWU input source or RESET pin
Table continues on the next page...
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1120 NXP Semiconductors