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Table 44-2. Power mode transition triggers (continued)
Transition #
From
To
Trigger conditions
9
VLPR
VLLSx
PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit
modes entered with SLEEPDEEP set, which is controlled in
System Control Register in Arm core.
10
RUN
LLSx
PMPROT[ALLS]=1, PMCTRL[STOPM]=011,
STOPCTRL[LLSM]=x (LLSx), Sleep-now or sleep-on-exit
modes entered with SLEEPDEEP set, which is controlled in
System Control Register in Arm core.
LLSx
RUN
Wakeup from enabled LLWU input source and LLSx mode
was entered directly from RUN or
RESET pin.
11
VLPR
LLSx
PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or
sleep-on-exit modes entered with SLEEPDEEP set, which is
controlled in System Control Register in Arm core.
LLSx
VLPR
Wakeup from enabled LLWU input source and LLSx mode
was entered directly from VLPR
NOTE: If LLSx was entered directly from RUN, hardware will
not allow this transition and will force exit back to
RUN
12
RUN
HSRUN
Set PMPROT[AHSRUN]=1, PMCTRL[RUNM]=11.
HSRUN
RUN
Set PMCTRL[RUNM]=00 or
Reset
1. If debug is enabled, the core clock remains to support debug.
2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP
3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If
PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS
44.4.2 Power mode entry/exit sequencing
When entering or exiting low-power modes, the system must conform to an orderly
sequence to manage transitions safely.
The SMC manages the system's entry into and exit from all power modes. This diagram
illustrates the connections of the SMC with other system components in the chip that are
necessary to sequence the system through all power modes.
Chapter 44 System Mode Controller (SMC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors
1121
Summary of Contents for K32 L2A Series
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