NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1221 / 1379

48.1.3.3.4.2 Function
The TRNG0 Poker Range Register defines the difference between the TRNG Poker
Maximum Limit and the minimum limit. These limits are used during the TRNG
Statistical Check Poker Test.
48.1.3.3.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PKR_RNG
W
Reset
0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1
48.1.3.3.4.4 Fields
Field Function
31-16
—
Reserved. Always 0.
15-0
PKR_RNG
Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which requires a maximum and
minimum limit. The maximum is programmed in the PKRMAX[PKR_MAX] register, and the minimum is
derived by subtracting the PKR_RNG value from the programmed maximum value. This field is writable
only if TRNG0_MCTL[PRGM] bit is 1. This field will read zeroes if TRNG0_MCTL[PRGM] = 0. This field is
cleared to the default POR value by writing the TRNG0_MCTL[RST_DEF] bit to 1. Note that the minimum
allowable Poker result is PKR_MAX - P 1.
48.1.3.3.5 TRNG0 Poker Maximum Limit (TRNG0_PKRMAX)
48.1.3.3.5.1 Address
Register Offset Description
TRNG0_PKRMAX 400A500Ch Accessible at this address when
TRNG0_MCTL[PRGM] = 1]
Chapter 48 SA-TRNG Standalone
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1221